Field of the Disclosure
The present invention relates to an array substrate for a liquid crystal display (LCD) device and more particularly to an array substrate for an LCD device having improved properties and being capable of preventing a photo leakage current problem, and a method of fabrication the array substrate.
Description of the Related Art
A related art liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite alignment direction as a result of their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field across the liquid crystal molecules. In other words, as the intensity or direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Since incident light is refracted based on the orientation of the liquid crystal molecules due to the optical anisotropy of the liquid crystal molecules, images can be displayed by controlling light transmissivity.
Since the LCD device including a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent characteristics of high resolution and displaying moving images, the AM-LCD device has been widely used.
FIG. 1 is a plan view of a pixel region of the related art array substrate for the LCD device. In FIG. 1, a gate line 20 and a data line 30 are formed on a substrate 10. The gate and data lines 20 and 30 cross each other to define a pixel region “P”. A thin film transistor (TFT) “T” is formed at a crossing portion of the gate and data lines 20 and 30. The TFT “T” includes a gate electrode 25, a semiconductor layer (not shown), a source electrode 32 and a drain electrode 34. The gate electrode 25 extends from the gate line 20, and the semiconductor layer is formed over the gate electrode 25 to overlap the gate electrode 25. The source electrode 32 extends from the data line 30 and is spaced apart from the drain electrode 34. The source and drain electrodes 32 and 34 contact the semiconductor layer. Although not shown, the semiconductor layer includes an active layer of intrinsic amorphous silicon and an ohmic contact layer of impurity-doped amorphous silicon. In addition, a pixel electrode 70 contacting the drain electrode 34 through a drain contact hole “CH1”, which exposes a portion of the drain electrode 34, is formed in the pixel region “P”.
Referring to FIGS. 2A to 2G, a method of fabricating the related art array substrate is explained. FIGS. 2A to 2G are cross-sectional views showing a fabricating process of a portion taken along the line II-II′ in FIG. 1. A region, where the TFT is formed, is defined as a switching region “S(T)”.
FIG. 2A shows a first mask process. In FIG. 2A, a first metal layer (not shown) is formed on the substrate 10 by depositing a conductive metallic material. The conductive metallic material includes copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd) and chrome (Cr). The first metal layer is patterned using a first mask (not shown) to form the gate line 20 (of FIG. 1) and the gate electrode 25. The gate electrode 25 extends from the gate line 20 (of FIG. 1) and is disposed in the switching region “S(T)”. Next, a gate insulating layer 45 is formed on the substrate 10, where the gate line 20 (of FIG. 1) and the gate electrode 25 are formed, by depositing an inorganic insulating material. The inorganic insulating material includes silicon oxide (SiO2) and silicon nitride (SiNx).
FIGS. 2B and 2C show a second mask process. In FIG. 2B, an intrinsic amorphous silicon layer 40a of intrinsic amorphous silicon and an impurity-doped amorphous silicon layer 41a of impurity-doped amorphous silicon are sequentially formed on the gate insulating layer 45. The intrinsic amorphous silicon layer 40a and the impurity-doped amorphous silicon layer 41 a have first and second thickness, respectively. For example, the first thickness of the intrinsic amorphous silicon layer 40a may be about 1500 angstroms to about 2000 angstroms, and the second thickness of the impurity-doped amorphous silicon layer 41a may be about 500 angstroms to about 1000 angstroms. Namely, the intrinsic amorphous silicon layer 40a has a greater thickness than the impurity-doped amorphous silicon layer 41a. For example, a thickness of the intrinsic amorphous silicon layer 40a may be nearly five times as much as that of the impurity-doped amorphous silicon layer 41a. 
In FIG. 2C, the intrinsic amorphous silicon layer 40a (of FIG. 2B) and the intrinsic amorphous silicon layer 40a (of FIG. 2B) are patterned using a second mask (not shown) to form an active layer 40 and an ohmic contact layer 41. The active layer 40 overlaps the gate electrode 25, and the ohmic contact layer 41 is disposed on the active layer 40. The active layer 40 and the ohmic contact layer 41 have the same plane area as each other. The active layer 40 and the ohmic contact layer 41 constitute a semiconductor layer 42.
FIGS. 2D and 2E show a third mask process. In FIG. 2D, a second metal layer (not shown) is formed on the semiconductor layer 42 by depositing a conductive metallic material. The conductive metallic material includes copper (Cu), molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd) and chrome (Cr). The second metal layer is patterned using a third mask (not shown) to form the data line 30, the source electrode 32 and the drain electrode 34. The data line 30 crosses the gate line 20 (of FIG. 1) to define the pixel region “P”. The source electrode 32 extends from the data line 30 and is spaced apart from the drain electrode 34. As a result, a portion of the ohmic contact layer 41 is exposed between the source and drain electrodes 32 and 34.
Next, in FIG. 2E, the exposed portion of the ohmic contact layer 41 is etched by a dry-etching process using the source and drain electrodes 32 and 34 as an etching mask to expose a portion of the active layer 40. The portion of the active layer 40 is over-etched to form a back-etch type channel “ch”. The gate electrode 25, the gate insulating layer 45, the semiconductor layer 42, which includes the active layer 40 and the ohmic contact layer 41, the source electrode 32 and the drain electrode 34 constitute the TFT “T” (of FIG. 1) in the switching region “S(T)”.
FIG. 2F shows a fourth mask process. In FIG. 2F, a passivation layer 55 is formed on the data line 30, the source electrode 32 and the drain electrode 34. The passivation layer 55 includes one of an inorganic insulating material, such as silicon nitride and silicon oxide, and an organic insulating material, such as acryl-based resin and benzocyclobutene (BCB). The passivation layer 55 is patterned using a fourth mask (not shown) to form a drain contact hole “CH1” exposing a portion of the drain electrode 34.
FIG. 2G shows a fifth mask process. In FIG. 2G, a transparent conductive metal layer (not shown) is formed on the passivation layer 55 including the drain contact hole “CH1”. The transparent conductive metal layer includes a transparent conductive material, for example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The transparent conductive metal layer is patterned using a fifth mask (not shown) to form the pixel electrode 70 in the pixel region “P”. The pixel electrode 70 contacts the drain electrode 34 through the drain contact hole “CH1”.
The related art array substrate for the LCD device is fabricated by the above-mentioned five mask process. In the related art array substrate, the active layer 40 has a greater thickness than the ohmic contact layer 41 to obtain the back-etch type channel “ch”. As mentioned above, a thickness of the intrinsic amorphous silicon layer 40a may be nearly five times as much as that of the impurity-doped amorphous silicon layer 41a. When there is a process error in etching the exposed ohmic contact layer 41 and the active layer 40 to form the back-etch type channel “ch”, not only the active layer 40 but also the gate insulating layer 45 may have an damage such that properties of the TFT are degraded. To prevent these problems, the active layer 40 has a greater thickness than the ohmic contact layer 41.
However, the active layer 40 having the relatively high thickness causes resistance between the source electrode 32 and the channel “ch” or/and between drain electrode 34 and the channel “ch” to be increased. As a result, properties of the TFT “T” are degraded. Particularly, the greater thickness the active layer 40 has, the much photo leakage current there is. The photo leakage current is generated when the active layer 40 is exposed to the light from a backlight unit or the ambient light. The photo leakage current causes the properties of the TFT “T” to be degraded. Moreover, the photo leakage current causes a cross-talk problem such that a displaying image quality in the LCD device is also degraded. Furthermore, the great thickness of the active layer 40 requires the production time and the initial investment for the machine to be increased. Namely, productivity is decreased.